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NCP1252 Current Mode PWM Controller for Forward and Flyback Applications
The NCP1252 controller offers everything needed to build cost- effective and reliable ac-dc switching supplies dedicated to ATX power supplies. Thanks to the use of an internally fixed timer, NCP1252 detects an output overload without relying on the auxiliary Vcc. A Brown-Out input offers protection against low input voltages and improves the converter safety. Finally a SOIC8 package saves PCB space and represents a solution of choice in cost sensitive project.
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OFFLINE CONTROLLER
* * * * * * * * * * * * * * * * *
Peak Current Mode Control Adjustable Switching Frequency up to 500 kHz Jittering Frequency 5% of the Switching Frequency Latched Primary Over Current Protection with 10 ms Fixed Delay Delayed Operation Upon Start-up via an Internal Fixed Timer Adjustable Soft-start Timer Auto-recovery Brown-Out Detection UC384X-like UVLO Thresholds Vcc Range from 9 V to 28 V with Auto-recovery UVLO Internal 160 ns Leading Edge Blanking Adjustable Internal Ramp Compensation +500 mA / -800 mA Source / Sink Capability Maximum 50% Duty Cycle: A Version Maximum 80% Duty Cycle: B Version Ready for Updated No Load Regulation Specifications SOIC-8 Package This is a Pb-Free Device
8 1 SOIC-8 CASE 751 SUFFIX D
PIN CONNECTIONS
FB BO CS RT (Top View) 1 SS VCC DRV GND
MARKING DIAGRAM
8 1252X ALYWX G
Typical Applications
1 1252 X A L Y W G
* Power Supplies for PC Silver Boxes, Games Adapter... * Flyback and Forward Converter
= Specific Device Code = A or B Version = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
April, 2009 - Rev. 1
1
Publication Order Number: NCP1252/D
NCP1252
Vbulk
Vout NCP1252 1 2 3 4 8 7 6 5 Vcc
Table 1. PIN FUNCTIONS
Pin No. 1 2 3 4 5 6 7 8 Pin Name FB BO CS RT GND Drv VCC SSTART Function Feedback Brown-out input Current sense Timing element - Driver VCC Soft-start Pin Description This pin directly connects to an optocoupler collector. This pin monitors the input voltage image to offer a Brown-out protection. Monitors the primary current and allows the selection of the ramp compensation amplitude. A resistor connected to ground fixes the switching frequency. The controller ground pin. This pin connects to the MOSFET gate This pin accepts voltage range from 8 V up to 28 V A capacitor connected to ground selects the soft-start duration. The soft start is grounded during the delay timer
Table 2. MAXIMUM RATINGS TABLE (Notes 1 and 2)
Symbol VCC VCC IVcc RJ-A - SO TJMAX Rating Power Supply voltage, Vcc pin, transient voltage: 10 ms with IVcc < 20 mA Power Supply voltage, Vcc pin, continuous voltage Maximum current injected into pin 7 Maximum voltage on low power pins (except pin 6, 7) Thermal Resistance Junction-to-Air - SO8 Maximum Junction Temperature Storage Temperature Range ESD Capability, HBM model ESD Capability, Machine Model Value 30 28 20 -0.3 to 10 180 150 -60 to +150 1.8 200 Unit V V mA V C/W C C kV V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1800 V per JEDEC Standard JESD22-A114E. Machine Model Method 200 V per JEDEC Standard JESD22-A115A. 2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
Table 3. ORDERING INFORMATION
Device NCP1252ADR2G NCP1252BDR2G Version A version B version Marking 1252A 1252B Shipping 2500/Tape & Reel 2500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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SQ Q R 3.5V 0V Buffered Ramp Grand Fs w Reset selection fs w Jittering Ct 30 V UVLO reset Vcc management RT
QS Q R 2 bits counter End Reset Set Active Clamp 15V Boot strap 15V - 2R + SQ Q R
UVLO
Out Count Fault Timer clk Reset 10 kHz
RT
Vcc
Vdd - Vskip Fs wing
+
Clock
Drv
FB R
NCP1252
IBO Hyst. VBO
+
s hutdown
-
Figure 1. Internal Circuit Architecture
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Rr amp - 1V (FCS) + BO BOK - LEB CS Buffered Ramp + MaxDC UV LO r eset
3
GND
Rcomp
Rsense
Vbulk
Note: MaxDC = 50% with A version MaxDC = 80% with B version Soft Start Status Vdd Fix ed Delay Iss UV LO 120 ms
SST ART Grand Reset Grand Reset
Soft start
NCP1252
Table 4. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25C, for min/max values TJ = -25C to +125C, unless otherwise noted) Characteristics SUPPLY SECTION AND VCC MANAGEMENT Startup threshold at which driving pulses are authorized Minimum Operating voltage at which driving pulses are stopped Hysteresis between VCC(on) and VCC(min) Start-up current, controller disabled Internal IC consumption, controller switching Internal IC consumption, controller switching CURRENT COMPARATOR Current Sense Voltage Threshold Leading Edge Blanking Duration Input Bias Current Propagation delay Internal Ramp Compensation Voltage level Internal Ramp Compensation resistance to CS pin INTERNAL OSCILLATOR Oscillator Frequency Oscillator Frequency Frequency Modulation in percentage of fOSC Frequency modulation Period Maximum operating frequency Maximum duty-cycle - A version Maximum duty-cycle - B version FEEDBACK SECTION Internal voltage division from FB to CS setpoint Internal pull-up resistor FB pin maximum current Internal feedback impedance from FB to GND Open loop feedback voltage Internal Diode forward voltage DRIVE OUTPUT DRV Source resistance DRV Sink resistance Output voltage rise-time 3. Guaranteed by design 4. Vramp, Rramp Guaranteed by design VCC = 15 V, CDRV = 1nF, 10 to 90% RSRC RSINK tr - - - 10 6 26 30 19 - W W ns FB pin = open (Note 3) FB pin = GND FBdiv Rpull-up IFB ZFB VFBOL Vf - - 1.5 - - - 3 3.5 - 40 6.0 0.75 - - - - - - - kW mA kW V V RT = 43 kW & DRV pin = 47 kW RT = 8.5 kW & DRV pin = 47 kW (Note 3) (Note 3) (Note 3) fOSC fOSC fjitter Tswing fMAX DCmaxA DCmaxB 92 425 - - 500 45.6 76 100 500 5 3.33 - 48 80 108 550 - - - 49.6 84 kHz kHz % ms kHz % % (Note 3) From CS detected to gate turned off @ 25C (Note 4) @ 25C (Note 4) VILIM tLEB Ibias tILIM Vramp Rramp 0.92 - - - 3.15 - 1 160 0.02 70 3.5 26.5 1.08 - - 150 3.85 - V ns mA ns V kW VCC < VCC(on) & VCC increasing from zero Fsw =100 kHz, DRV = open Fsw =100 kHz, CDRV = 1 nF VCC increasing VCC decreasing VCC(on) VCC(off) VCC(HYS) ICC1 ICC2 ICC3 9.4 8.4 0.9 - 0.5 2.0 10 9 1.0 - 1.4 2.7 10.6 9.6 - 100 2.2 3.5 V V V mA mA mA Test Condition Symbol Min Typ Max Unit
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Table 4. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25C, for min/max values TJ = -25C to +125C, unless otherwise noted) Characteristics DRIVE OUTPUT Output voltage fall-time Clamping voltage (maximum gate voltage) High-state voltage drop CYCLE SKIP Skip cycle level Skip threshold Reset Skip threshold Hysteresis SOFT START Soft-start charge current Soft start completion voltage threshold Internal delay before starting the Soft start when VCC(on) is reached PROTECTION Current sense fault voltage level triggering the timer Timer delay before latching a fault (overload or short circuit) Brown-out voltage Internal current source generating the Brown-out hysteresis 3. Guaranteed by design 4. Vramp, Rramp Guaranteed by design -5C TJ +125C -25C TJ +125C When CS pin > FCS FCS Tfault VBO IBO 0.9 10 0.974 8.8 8.6 1 15 1 10 10 1.1 20 1.026 11.2 11.2 V ms V mA SS pin = GND ISS VSS SSdelay 8.8 3.5 100 10 4.0 120 11 4.5 155 mA V ms Vskip Vskip(reset) Vskip(HYS) 0.2 - - 0.3 Vskip+ Vskip(HYS) 25 0.4 - - V V mV VCC = 15 V, CDRV = 1nF, 90 to 10% VCC = 25 V RDRV = 47 kW, CDRV = 1 nF VCC = VCC(min) + 100 mV, RDRV = 47 kW, CDRV = 1 nF tf VCL VDRV(clamp) - - - 22 15 50 - 18 500 ns V mV Test Condition Symbol Min Typ Max Unit
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE HYSTERESIS LEVEL (V) UNDER VOLTAGE LOCK OUT LEVEL (V) 10.2 10.0 9.8 9.6 9.4 9.2 9.0 8.8 -40 -20 0 20 VCC(off) 40 60 80 100 120 VCC(on) 1.20 1.15 1.10 1.05 1.00 0.95 0.90 -40 -20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 2. Supply Voltage Threshold vs. Junction Temperature
Figure 3. Supply Voltage Hysteresis vs. Junction Temperature
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TYPICAL CHARACTERISTICS
50 STARTUP CURRENT ICC1 (mA) SUPPLY CURRENT ICC3 (mA) 120 40 30 20 10 0 -40 -20 5 4 3 2 1 0 -40 -20
0
20
40
60
80
100
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 4. Start-up Current (ICC1) vs. Junction Temperature
4 SUPPLY CURRENT ICC3 (mA) CURRENT SENSE VOLTAGE THRESHOLD (V) 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 -40
Figure 5. Supply Current (ICC3) vs. Junction Temperature
3
2
1
0
10
15
20
25
30
-20
0
20
40
60
80
100
120
SUPPLY VOLTAGE Vcc (V)
TEMPERATURE (C)
Figure 6. Supply Current (ICC3) vs. Supply Voltage
LEADING EDGE BLANKING TIME (ns) LEADING EDGE BLANKING TIME (ns) 300 250 200 150 100 50 0 -40 -20 300 250 200 150 100 50 0
Figure 7. Current Sense Voltage Threshold vs. Junction Temperature
0
20
40
60
80
100
120
10
15
20
25
30
TEMPERATURE (C)
SUPPLY VOLTAGE Vcc (V)
Figure 8. Leading Edge Blanking Time vs. Junction Temperature
Figure 9. Leading Edge Blanking Time vs. Supply Voltage
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NCP1252
TYPICAL CHARACTERISTICS
160 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 160 140 120 100 80 60 40 20 0 10 15 20 25 30
TEMPERATURE (C)
SUPPLY VOLTAGE Vcc (V)
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
Figure 10. Propagation Delay from CS to DRV vs. Junction Temperature
108 106 104 102 100 98 96 94 92 -40 -20 0 20 40 60 80 100 120
Figure 11. Propagation Delay from CS to DRV vs. Supply Voltage
108 106 104 102 100 98 96 94 92 10 15 20 25 30
TEMPERATURE (C)
SUPPLY VOLTAGE Vcc (V)
Figure 12. Oscillator Frequency vs. Junction Temperature
SWITCHING FREQUENCY, FSW (kHz) 500 400 350 300 250 200 150 100 50 0 MAXIMUM DUTY CYCLE (%) 450 49
Figure 13. Oscillator Frequency vs. Supply Voltage
48
47
46
0
20
40
60
80
100
45 -40 -20
0
20
40
60
80
100
120
Rt RESISTOR (kW)
TEMPERATURE (C)
Figure 14. Oscillator Frequency vs. Oscillator Resistor
Figure 15. Maximum Duty-cycle, A Version vs. Junction Temperature
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TYPICAL CHARACTERISTICS
84 MAXIMUM DUTY CYCLE (%) DRIVE SINK AND SOURCE RESISTANCE (W) 83 82 81 80 79 78 77 76 -40 -20 0 20 40 60 80 100 120 14 12 10 ROH 8 6 4 2 0 -40 -20 0 20 40 60 80 100 120 ROL
TEMPERATURE (C)
TEMPERATURE (C)
Figure 16. Maximum Duty-cycle, B Version vs. Junction Temperature
20 DRIVE CLAMPING VOLTAGE (V) 18 16 14 12 10 -40 -20 DRIVE CLAMPING VOLTAGE (V) 20 18 16 14 12 10
Figure 17. Drive Sink and Source Resistances vs. Junction Temperature
0
20
40
60
80
100
120
10
15
20
25
30
TEMPERATURE (C)
SUPPLY VOLTAGE Vcc (V)
Figure 18. Drive Clamping Voltage vs. Junction Temperature
1.0 SKIP CYCLE THRESHOLD (V) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 SOFT START CURRENT (mA) 0.9 11
Figure 19. Drive Clamping Voltage vs. Supply Voltage
10
9
-20
0
20
40
60
80
100
120
8 -40 -20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 20. Skip Cycle Threshold vs. Junction Temperature
Figure 21. Soft Start Current vs. Junction Temperature
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TYPICAL CHARACTERISTICS
5.0 SOFT START COMPLETION VOLTAGE THRESHOLD (V) 1.10 1.08 4.5 BROWN OUT VOLTAGE THRESHOLD (V) 100 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 -40
4.0
3.5
3.0 -40 -20
0
20
40
60
80
120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 22. Soft Start Completion Voltage Threshold vs. Junction Temperature
BROWN OUT VOLTAGE THRESHOLD (V) 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 INTERNAL BROWN OUT CURRENT SOURCE (mA) 1.10 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5
Figure 23. Brown Out Voltage Threshold vs. Junction Temperature
10
15
20
25
30
8.0 -40 -20
0
20
40
60
80
100
120
SUPPLY VOLTAGE Vcc (V)
TEMPERATURE (C)
Figure 24. Brown Out Voltage Threshold vs. Supply Voltage
12.0 INTERNAL BROWN OUT CURRENT SOURCE (mA) 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 10 15 20
Figure 25. Internal Brown Out Current Source vs. Junction Temperature
25
30
SUPPLY VOLTAGE Vcc (V)
Figure 26. Internal Brown Out Current Source vs. BO Pin Voltage
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NCP1252
Application Information
Introduction
The NCP1252 hosts a high-performance current-mode controller specifically developed to drive power supplies designed for the ATX and the adapter market: * Current Mode operation: implementing peak current-mode control topology, the circuit offers UC384X-like features to build rugged power supplies. * Adjustable switching frequency: a resistor to ground precisely sets the switching frequency between 50 kHz and a maximum of 500 kHz. There is no synchronization capability. * Internal frequency jittering: Frequency jittering softens the EMI signature by spreading out peak energy within a band 5% from the center frequency. * Wide Vcc excursion: the controller allows operation up to 28 V continuously and accepts transient voltage up to 30 V during 10 ms with IVCC < 20 mA * Gate drive clamping: a lot of powers MOSFETs do not allow their driving voltage to exceed 20 V. The controller includes a low-loss clamping voltage which prevents the gate from going beyond 15 V typical. * Low startup-current: reaching a low no-load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. The start-up current is guaranteed to be less than 100 mA maximum, helping the designer to reach a low standby power level. * Short-circuit protection: by monitoring the CS pin voltage when it exceeds 1 V (maximum peak current), the controller detects a fault and starts an internal digital timer. On the condition that the digital timer elapses, the controller will permanently latch-off. This allows accurate overload or short-circuit detection which is not dependant on the auxiliary winding. Reset occurs when: a) a BO reset is sensed, b) VCC is cycled down to VCC(min) level. If the short circuit or the fault disappear before the fault timer ends, the fault timer is reset only if the CS pin voltage level is below 1 V at least during 3 switching frequency periods. This delay before resetting the fault timer prevents any false or missing fault or over load detection. * Adjustable soft-start: the soft-start is activated upon a start-up sequence (VCC going-up and crossing
*
*
*
*
VCC(on)) after a minimum internal time delay of 120 ms (SSdelay). But also when the brown-out pin is reset without in that case timer delay. This internal time delay gives extra time to the PFC to be sure that the output PFC voltage is in regulation. The soft start pin is grounded until the internal delay is ended. Shutdown: if an external transistor brings the BO pin down, the controller is shut down, but all internal biasing circuits are alive. When the pin is released, a new soft-start sequence takes place. Brown-Out protection: BO pin permanently monitors a fraction of the input voltage. When this image is below the VBO threshold, the circuit stays off and does not switch. As soon the voltage image comes back within safe limits, the pulses are re-started via a start-up sequence including soft-start. The hysteresis is implemented via a current source connected to the BO pin; this current source sinks a current (IBO) from the pin to the ground. As the current source status depends on the brown-out comparator, it can easily be used for hysteresis purposes. A transistor pulling down the BO pin to ground will shut-off the controller. Upon release, a new soft-start sequence takes place. Internal ramp compensation: a simple resistor connected from the CS pin to the sense resistor allows the designer to inject ramp compensation inside his design. Skip cycle feature: When the power supply loads are decreasing to a low level, the duty cycle also decreases to the minimum value the controller can offer. If the output loads disappear, the converter runs at the minimum duty cycle fixed by the propagation delay and driving blocks. It often delivers too much energy to the secondary side and it trips the voltage supervisor. To avoid this problem, the FB is allowed to impose the min tON down to ~ Vf and it further decreases down to Vskip, zero duty cycle is imposed. This mode helps to ensure no-load outputs conditions as requested by recently updated ATX specifications. Please note that the converter first goes to min tON before going to zero duty cycle: normal operation is thus not disturbed. The following figure illustrates the different mode of operation versus the FB pin level.
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NCP1252
FB level
VFBOL = 6.0 V Normal Operation: DCmin < DC < DCmaxA/B
Vf = 0.75 V Vskip = 0.3 V
Operation @ Ton_min DC = DCmin Skip: DC = 0% Time
Figure 27. Mode of Operation versus the FB Pin Level Startup Sequence:
The startup sequence is activated when Vcc pin reaches VCC(on) level. Once the startup sequence has been activated the internal delay timer (SSdelay) runs. Only when the internal delay elapses the soft start can be allowed if the BO pin level is above VBO level. If the BO pin threshold is reached or as soon as this level will be reached the soft start
VCC pin VCC(on)
is allowed. When the soft start is allowed the SS pin is released from the ground and the current source connected to this pin sources its current to the external capacitor connected on SS pin. The voltage variation of the SS pin divided by 4 gives the same peak current variation on the CS pin. The following figures illustrate the different startup cases.
VCC pin VCC(on)
BO pin
Time
BO pin
Time
VBO Time SS pin 120 ms: Internal delay DRV pin Soft start Time
VBO SS pin Time
120 ms: Internal delay DRV pin Soft start Time
No pulse CASE #1 Time CASE #2 Time
Figure 28. Different Startup Sequence Case #1 & #2
With the Case #1, when the VCC pin reaches the VCC(on) level, the internal timer starts. As the BO pin level is above the VBO threshold at the end of the internal delay, a soft start sequence is started.
With the Case #2, at the end of the internal delay, the BO pin level is below the VBO threshold thus the soft start sequence can not start. A new soft start sequence will start only when the BO pin reaches the VBO threshold.
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NCP1252
VCC pin VCC(on) VCC pin VCC(on)
BO pin VBO
Time
BO pin VBO
Time
SS pin SS capacitor is discharged
Time
SS pin
Soft start
Time
DRV pin
Time
DRV pin
Time
CASE #3
Time
CASE #4
Time
Figure 29. Controller Shuts Down with the Brown Out Pin
When the BO pin is grounded, the controller is shut down and the SS pin is internally grounded in order to discharge the soft start capacitor connected to this pin (Case #3). If the BO pin is released, when its level reaches the VBO level a new soft start sequence happens.
Soft Start:
As illustrated by the following figure, the rising voltage on the SS pin voltage divided by 4 controls the peak current sensed on the CS pin. Thus as soon as the CS pin voltage becomes higher than the SS pin voltage divided by 4 the driver latch is reset.
Clock S LEB
Rcomp Rse nse
CS
Q Q
DRV
Soft Start Status Vdd Iss Fixe d Delay 120 ms UVLO
R
+ -
SS Soft start
1/4 Grand Reset
Figure 30. Soft Start Principle
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The following figure illustrates a soft start sequence.
Soft Start pin (2 V/div)
TSS = 13 ms
VSS = 4 V
CS pin (0.5 V/div)
Time (4 ms/div)
Figure 31. Soft Start Example Brown-Out Protection
By monitoring the level on BO pin, the controller protects the forward converter against low input voltage conditions. When the BO pin level falls below the VBO level, the controllers stops pulsing until the input level goes back to normal and resumes the operation via a new soft start sequence.
The brown-out comparator features a fixed voltage reference level (VBO). The hysteresis is implemented by using the internal current connected between the BO pin and the ground when the BO pin is below the internal voltage reference (VBO).
S Q Q
Vbulk RB O u p shutdown BO + - RB Olo VBO IBO R BOK
UVLO r eset
Grand Reset
Figure 32. BO Pin Setup
The following equations show how to calculate the resistors for BO pin. First of all, select the bulk voltage value at which the controller must start switching (Vbulkon) and the bulk voltage for shutdown (Vbulkoff) the controller. Where: * Vbulkon = 370 V * Vbulkoff = 350 V * VBO = 1 V * IBO = 10 mA When BO pin voltage is below VBO (internal voltage reference), the internal current source (IBO) is activated. The following equation can be written:
V bulkON + R BOup I BO )
V BO ) V BO R BOlo
(eq. 1)
When BO pin voltage is higher than VBO, the internal current source is now disabled. The following equation can be written:
V BO + V bulkoffR BOlo R BOlo ) R BOup
(eq. 2)
From Equation 2 it can be extracted the RBOup:
R BOup + V bulkoff * V BO R BOlo V BO
(eq. 3)
Equation 3 is substituted in Equation 1 and solved for RBOlo, yields:
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NCP1252
R BOlo + V BO V bulkon * V BO *1 I BO V bulkoff * V BO
(eq. 4)
Short Circuit or Over Load Protection:
RBOup can be also written independently of RBOlo by substituting Equation 4 into Equation 3 as follow:
R BOup + V bulkon * V bulkoff I BO
(eq. 5)
From Equation 4 and Equation 5, the resistor divider value can be calculated:
R BOlo + 1 370 * 1 * 1 + 5731 W 10 m 350 * 1 R BOup + 370 * 350 + 2.0 MW 10 m
A short circuit or an overload situation is detected when the CS pin level reaching its maximum level at 1 V. In that case the fault status is stored in the latch and allows the digital timer count. If the digital timer ends then the fault is latched and the controller permanently stops the pulses on the driver pin. If the fault is gone before ending the digital timer, the timer is reset only after 3 switching controller periods without fault detection (or when the CS pin < 1 V during at least 3 switching periods). If the fault is latched the controller can be reset if a BO reset is sensed or if VCC is cycled down to VCC(off).
Fault timer: 15 ms CS pin (500 mV/div)
Short Circuit
12 Vout (5 V/div)
Time (4 ms/div)
Figure 33. Short Circuit Detection Example Shut Down
There is one possibility to shut down the controller; this possibility consists at grounding the BO pin as illustrated in Figure 32.
Ramp Compensation
Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half of the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty-cycle close to and above 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. depicts how internally the ramp is generated: The ramp compensation applied on CS pin is from the internal oscillator ramp buffered. A switch placed between the buffered internal oscillator ramp and Rramp disconnects the ramp compensation during the OFF time DRV signal.
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NCP1252
Vdd FB 2R R Clock S Q Q DRV path
Buffered Ramp Rramp + LEB - Rcomp Rsense CS Ccs
R
Figure 34. Ramp Compensation Setup
In the NCP1252, the internal ramp swings with a slope of:
S int + V ramp F DC max SW
(eq. 6)
A few line of algebra determined Rcomp:
R comp + R ramp Ratio 1 * Ratio
(eq. 9)
In a forward application the secondary-side downslope viewed on a primary side requires a projection over the sense resistor Rsense. Thus:
S sense + (V out ) V f) N s R L out N p sense
(eq. 7)
where: * Vout is output voltage level * Vf the freewheel diode forward drop * Lout, the secondary inductor value * Ns/Np the transformer turn ratio * Rsense: the sense resistor on the primary side Assuming the selected amount of ramp compensation to be applied is comp, then we must calculate the division ratio to scale down Sint accordingly:
Ratio + R sensed comp S int
(eq. 8)
The previous ramp compensation calculation does not take into account the natural primary ramp created by the transformer magnetizing inductance. In some case illustrated here after the power supply does not need additional ramp compensation due to the high level of the natural primary ramp. The natural primary ramp is extracted from the following formula:
S natural + V bulk R L mag sense S natural S sense
(eq. 10)
Then the natural ramp compensation will be:
d natural_comp +
(eq. 11)
If the natural ramp compensation (natural_comp) is higher than the ramp compensation needed (comp), the power supply does not need additional ramp compensation. If not, only the difference (comp-natural_comp) should be used to calculate the accurate compensation value.
Thus the new division ratio is:
if d natural_comp t d comp a Ratio + S sense(d comp * d natural_comp) S int
(eq. 12)
Then Rcomp can be calculated with the same equation used when the natural ramp is neglected (Equation 9).
Ramp Compensation Design Example:
* Vbulk = 350 V, minimum input voltage at which the * * * * *
power supply works. Duty cycle max: DCmax = 84% Vramp = 3.5 V, Internal ramp level. Rramp = 26.5 kW, Internal pull-up resistance Targeted ramp compensation level: 100% Transformer specification: - Lmag = 13 mH - Ns/Np = 0.085
* * * * *
2 switch-Forward Power supply specification: Regulated output: 12 V Lout = 27 mH Vf = 0.7 V (drop voltage on the regulated output) Current sense resistor : 0.75 W Switching frequency : 125 kHz
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Internal ramp compensation level
S int + V ramp F a S int + 3.5 125 kHz + 520 mV 0.84 DC max sw ms
Secondary-side downslope projected over the sense resistor is:
S sense + (V out ) V f) N s (12 ) 0.7) R a S sense + 0.085 L out N p sense 27 @ 10 -6 0.75 + 29.99 mV ms
Natural primary ramp:
S natural + V bulk R a S natural + 350 -3 0.75 + 20.19 mV L mag sense 13 @ 10 S natural a d natural_comp + 20.19 + 67.3% 29.99 S sense ms
Thus the natural ramp compensation is:
d natural_comp +
Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be added to prevent sub-harmonics oscillation.
Ratio + S sense(d comp * d natural_comp) S int a Ratio + 29.99 @ (1.00 * 0.67) + 0.019 520
We can know calculate external resistor (Rcomp) to reach the correct compensation level.
R comp + R ramp
Ratio a R 0.019 + 509 W 3 comp + 26.5 @ 10 1 * 0.019 1 * Ratio
Thus with Rcomp = 510 W, 100% compensation ramp is applied on the CS pin. The following example illustrates a power supply where the natural ramp offers enough ramp compensation to avoid external ramp compensation. 2 switch-Forward Power supply specification: * Regulated output: 12 V * Duty cycle max: DCmax = 84% * Lout = 27 mH * Vramp = 3.5 V, Internal ramp level. * Vf = 0.7 V (drop voltage on the regulated output) * Rramp = 26.5 kW, Internal pull-up resistance * Current sense resistor: 0.75 W * Targeted ramp compensation level: 100% * Switching frequency: 125 kHz * Transformer specification: - Lmag = 7 mH * Vbulk = 350 V, minimum input voltage at which the - Ns/Np = 0.085 power supply works. Secondary-side downslope projected over the sense resistor is:
S sense + (V out ) V f) N s (12 ) 0.7) R a S sense + 0.085 L out N p sense 27 @ 10 -6 S natural + 0.75 + 29.99 mV ms
The natural primary ramp is:
V bulk R a S natural + 350 -3 0.75 + 37.5 mV L mag sense 7 @ 10 S natural a d natural_comp + 37.5 + 125% 29.99 S sense ms
And the natural ramp compensation will be:
d natural_comp +
So in that case the natural ramp compensation due to the magnetizing inductance of the transformer will be enough to prevent any sub-harmonics oscillation in case of duty cycle above 50%.
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16
NCP1252
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
A
8 5
-X-
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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17
NCP1252/D

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